[OT] Hardware Info Help

[Stuart Biggerstaff]

I think just a couple of things, and you've said this better than...

At 03:14 PM 1/8/03 -0800, Aaron Grewell wrote:
>Well, let me see if I can get this right.  L1 cache is always built into
>the processor.  It's very fast but there isn't much of it, used to keep
>very frequently used information close at hand.  L2 cache is usually
>built into modern processors.  With the notable exception of the
>original Celeron it's been built in since the Pentium.

Actually, wasn't it the Pentium Pro that introduced two levels of on-chip 
cache to the x86?  And it proved expensive for Intel to make, so the PII 
included L2 within the packaging but not technically on the chip.

>With 386 and 486
>processors L2 was optional, one of the features of a more expensive
>motherboard.

Wasn't on-chip cache (along with the on-chip math co-processor--disabled in 
SX models) the difference between the 386 and 486?

>It's not as fast as L1, but is a lot bigger.  Stuff that's
>used less often or is too big to fit in L1 will go into L2.  L3 is
>unusual in the desktop market.  The K6-III had it, but it's the only one
>I know of.

K6-III only had L3 because it had an on-chip L2 but was designed for socket 
7 MBs that usually included L2--which became L3.

>   It was what made that chip the last word in Socket 7
>architecture, and also entirely too expensive for AMD to produce.  Xeons
>and other high-end server chips (PA-RISC, SPARC, et al)

And apparently G3-G4s.

>have it as
>well.  It's only needed when lots of data is being thrown around,
>otherwise the extra cost isn't worth it.  It is larger but slower than
>L2.  Clever cache management is one of the features most important in a
>chip, and nowhere is that more clear than in a server chip that has 3
>kinds to choose from and has to figure out where best to store its
>dataset.



Stuart Biggerstaff

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